Data communication systems are constantly adapted to serve the ever-increasing need for high-speed data communication. For example, data transmitters of data communication systems have been adapted to transmit multi-level data signals having more than two amplitude levels to increase the transmission capacity of the data transmitter, thereby achieving higher speed for the data communication system.
Typically, to achieve higher speeds, data transmitters transmit the multi-level data signal without an accompanying clock signal. The absence of the accompanying clock signal may result in under-sampling or over-sampling of the multi-level data signal by a data receiver of the data communication system. Further, during long-distance transmission over a lossy communication channel, the multi-level data signal undergoes high attenuation due to noise and inter-symbol interference (ISI). Therefore, data receivers are usually equipped with a CDR circuit that generates a clock signal that is phase and frequency synchronized with the multi-level data signal and correctly detects the amplitude levels of the multi-level data signal by using the generated clock signal.
Some existing CDR circuits require a prior knowledge of the amplitude levels that are used to encode the sequential pairs of bits. When the amplitude levels that are used to encode the sequential pairs of bits are unknown and the multi-level data signal received by the data receiver is highly attenuated, these existing CDR circuits may not operate efficiently and may result in incorrect detection of the amplitude levels of the multi-level data signal.
Similarly, some existing CDR circuits typically operate by detecting transitions (i.e., rising and falling edges) within the multi-level data signal. However, when the multi-level data signal is attenuated by the ISI, a current amplitude level of the multi-level data signal overlaps with a previous amplitude level and anext amplitude level, and hence the transitions within the multi-level data signal may not be accurate. Consequently, these existing CDR circuits detect the amplitude levels of the data signal incorrectly, and are thus not suitable for implementing the data receiver that receives the multi-level data signal. These CDR circuits can cause instability issues in the data receiver that includes an analog-to-digital converter (ADC).
Typically, all communication channels vary in terms of loss profile. Therefore, data receivers require different CDR circuits that are suitable for the loss profile of the corresponding communication channel. Presently, a CDR circuit that operates accurately for all communication channels irrespective of their loss profiles is not available.